1. Field of the Invention
The present invention relates to a semiconductor device and a production method thereof, and more specifically, to a semiconductor device equipped with a capacitative element and a production method thereof.
2. Description of Related Art
As technologies related to semiconductor devices each equipped with a capacitative element of an MIM (Metal Insulator Metal) structure, there are those described by Patent document 1 to Patent document 3.
Patent document 1 describes a capacitative element formed on a semiconductor substrate directly or through a buffer layer. According to the document, it is assumed that by setting an area of an upper electrode smaller than an area of a lower electrode, leak and dielectric breakdown caused by thinning of the insulating film near a step part of the lower electrode can be suppressed. Moreover, as the insulating film that functions as a gate insulating film and as a capacitance film, a SiO2 film is exemplified, and as the insulating film on the upper electrode of the capacitative element, a SiO2 film and a SiNx film are exemplified.
Moreover, Patent document 2 describes a technology of forming a sidewall made up of a SiN film on a sidewall of the upper electrode of the capacitative element. It is assumed that by this technology, occurrence of side etching and etching damage of the dielectric film (capacitance film) right under an edge of the upper electrode can be prevented. Moreover, in terms of making it easy to set up the etching conditions, it is considered that preferably the side wall and the capacitance film are an identical insulating film.
Moreover, Patent document 3 describes a technology of providing a leak guard that is made up of an insulating material, such as plasma TEOS, so that it may cover an upper area and an edge area of the upper-layer electrode (the upper electrode) of the capacitative element. According to the document, it is assumed that by providing such a leak guard between the upper electrode and a reflection reducing film, the upper electrode and the reflection reducing film do not come in direct contact with each other, and therefore occurrence of leak current between the upper electrode and the lower-layer electrode layer (the lower electrode) can be prevented completely.    [Patent Document 1] Japanese Patent Laid Open Application No. 2005-159290    [Patent Document 2] Japanese Patent Laid Open Application No. 2003-258108    [Patent Document 3] Japanese Patent Laid Open Application No. 2003-318269
However, the present inventors have examined the above-mentioned conventional MIM capacity and have found that there is still a room of improvement on a side of suppressing a decrease in a withstand voltage.
Based on this finding, the present inventors have examined a cause of the decrease in the withstand voltage. FIG. 4 is a sectional view showing a configuration of a semiconductor device equipped with a capacitative element. In the semiconductor device shown in FIG. 4, a cap film 205, an interlayer insulating film 207, a cap film 213, an interlayer insulating film 215, an interlayer insulating film 217, a cap film 233, and an interlayer insulating film 235 are laminated on an upper part of the silicon substrate (unillustrated) sequentially from the bottom in this order. A lower electric wiring 211 and a lower electric wiring 209 are buried in the interlayer insulating film 207 and the cap layer 205, and an upper electric wiring 237 is buried in the interlayer insulating film 235 and the cap film 233.
Moreover, the capacitative element contacts the upper part of the interlayer insulating film 215, and is buried in the interlayer insulating film 217. The capacitative element is constructed with a lower electrode 219, an upper electrode 223, and a capacitance film 221 provided therebetween. The lower electrode 219 and the upper electric wiring 237 are being connected by a connecting plug 229, and the upper electrode 223 and the upper electric wiring 237 are being connected by a connecting plug 227. In order to connect the upper electrode 223 and the lower electrode 219 to the upper electric wiring 237, respectively, the upper electrode 223 has a structure where it overlaps a part of a formation area of the lower electrode 219. Moreover, the lower electric wiring 211 and the upper electric wiring 237 are being connected by a connecting plug 231.
In the manufacturing process of the semiconductor device shown in FIG. 4, after forming the conducting film that becomes the conducting film 219, the insulating film that becomes the capacitance film 221, and the conducting film that becomes the upper electrode 223 sequentially, the conducting film that becomes the upper electrode 223 is selectively removed by etching.
However, in the formation process of the upper electrode 223, as shown in FIG. 5, the inventors have found that there is a case where the insulating film that becomes the capacitance film 221 along the edge of the upper electrode 223 in the vicinity of the edge of the upper electrode 223 is overetched and a groove part 249 is formed. It is conjectured that by this mechanism, the periphery of the edge of the upper electrode 223 becomes a leakage path of the capacitance film and the withstand voltage decreases.